-- Vhdl LFSR Test Bench template for design : BCDtimer -- -- Simulation tool : ModelSim-Altera (VHDL) -- Vhdl LFSR Test Bench template for design : BCDtimer -- -- Simulation tool : ModelSim-Altera (VHDL) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.std_logic_textio.all; library std; use std.texto.all; entity lfsr_tb is end lfsr_tb; architecture lfsr_arch of lfsr_tb is constant PERIOD : time := 10 ns; signal clock : std_logic := '0'; signal reset : std_logic; signal enable : std_logic; signal lfsr_out : std_logic_vector (6 down to 0); signal seed : std_logic_vector (6 down to 0); signal resetsync : std_logic; signal random : std_logic_vector (3 down to 0); component lfsr is port ( -- reset : in std_logic; -- clk : in std_logic; -- lfsr_out : out std_logic_vector(6 downto 0) i_clk : in std_logic; i_rstb : in std_logic; i_sync_reset : in std_logic; i_seed : in std_logic_vector (6 downto 0); i_en : in std_logic; o_lsfr : out std_logic_vector (6 downto 0)); ); end component; type array_int7 is array (0 to 6) of integer; begin uut:lfsr port map ( --lista de conexiones entre los puertos maestros y las señales --clk => clock, --lsfr_out => lfsr_out, --reset => reset i_clk => clock, i_rstb => reset, i_sync_reset => resetsync, i_seed => seed, i_en => enable, o_lsfr => lfsr_out ); gen_clock : process (clock) begin clock <= not clock after PERIOD/2; end process; rnd <= lfsr_out (3 downto 0); init : PROCESS --Test de desempeño variable hits : array_init7; variable line_out : line; variable index : integer; BEGIN reset <= '1'; wait for PERIOD; reset <= '0'; --Inicializa contadores for i in 0 to 7 loop hits(i) := 0; end loop; --Secuencia del bucle for i in 1 to 127 loop wait for PERIOD; index := CONV_INTEGER(rnd); hits(index) := hits(index)+1; end loop; --Muestra por pantalla for i inn 0 to 6 loop write(line_out, CON_INTEGER(9, right, 1); write(line_out, string'(": ")); write(line_out, CONV_INTEGER(hits(i))); writeline(OUTPUT, line_out); hits(i) :=0; end loop; WAIT; end PROCESS init; end lfsr_arch;