entity control_logic is
 port (
  i_clk       : in  std_logic;
  i_rstb      : in  std_logic;
  -- input
  i_input    : in  std_logic;
  -- output
  o_output   : out std_logic);
end control_logic;

architecture rtl of control_logic is
type t_control_logic_fsm is (
				  ST_S0      ,
                          ST_S1      ,
                          ST_S2      ,
                          ST_S3      ,
				  ST_S4	 ,
                       	  ST_S5      ,
				  ST_S6

   );
signal r_st_present    : t_control_logic_fsm;
signal w_st_next       : t_control_logic_fsm;
begin
--------------------------------------------------------------------
-- FSM

p_comb : process(
                 r_st_present    ,
                 i_input        )
begin
  case r_st_present is
--------------- S0
    when ST_S0 => 
      if (i_input='1') then  
        w_st_next  <= ST_S2;
      else                                                         
        w_st_next  <= ST_S1;
      end if;
--------------- S1
    when ST_S1 => 
      if (i_input='1') then  
        w_st_next  <= ST_S2;
      else                                                         
        w_st_next  <= ST_S3;
      end if;
-------------- S2
    when ST_S2 => 
      if (i_input='1') then  
        w_st_next  <= ST_S4;
      else                                                         
        w_st_next  <= ST_S1;
      end if;
-------------- S3
    when ST_S3 => 
      if (i_input='1') then  
        w_st_next  <= ST_S2;
      else                                                         
        w_st_next  <= ST_S5;
      end if;
-------------- S4
    when ST_S4 => 
      if (i_input='1') then  
        w_st_next  <= ST_S6;
      else                                                         
        w_st_next  <= ST_S1;
      end if;
-------------- S5
    when ST_S5 => 
      if (i_input='1') then  
        w_st_next  <= ST_S2;
      else                                                         
        w_st_next  <= ST_S1;
      end if;
-------------- S6
    when ST_S6 => 
      if (i_input='1') then  
        w_st_next  <= ST_S2;
      else                                                         
        w_st_next  <= ST_S1;
      end if;
    when others=> => 
      w_st_next  <= ST_S0;
  end case;
end process p_comb;


p_state_out : process(i_clk,i_rstb)
begin
  if(i_rstb='0') then
    o_output     <= '0';
    r_st_present            <= ST_S0;
  elsif(rising_edge(i_clk)) then
    r_st_present            <= w_st_next;
    case r_st_present is
      when ST_S5        =>
        o_output     <= '0';
      when ST_S6        =>
        o_output     <= '1';
    end case;
  end if;
end process p_state_out;
end rtl;